The number and density of integrated circuit devices that require interconnection at the intrachip level continues to grow at a furious pace in accordance with Gordon Moore's famous prediction (i.e., the number of transistors per square inch on integrated circuits has doubled every 18 months since the integrated circuit was invented). The projected increase in integration density from millions of transistors on a single chip, to billions of transistors on a single chip, presents a significant challenge for intrachip interconnection techniques. The interconnection fabric—generally classified in terms of local, intermediate and global interconnections—must deliver power, communication signals and a low-skew clock signal to each and every one of the transistors and latches over an entire integrated circuit or microchip.
Multi-level wiring schemes have thus far served satisfactorily for the on-chip interconnections discussed above. However, these multi-level wiring schemes are currently being pushed to their technological limits as the number of integrated devices on a microchip continues to grow in accordance with Moore's Law. Thus, the need for even more levels of wiring seems inevitable. However, fundamental physical limits imposed by materials, devices, circuits, and systems indicate substantial challenges in interconnection technology could conceivably halt the progress of Very Large Scale Integrated (VLSI)/Ultra-Large Scale Integrated (ULSI) circuits.
Of particular concern are the global wire interconnections that carry communication signals, clock signals, and power between remotely separated regions of an integrated circuit. The requirements for these long point-to-point intrachip global interconnections are a growing design issue for integrated circuit and microchip manufacturers. Wires in global interconnections exhibit longer resistance-capacitance timing delays, greater clock skew, and higher power dissipation than their local and intermediate interconnection counterparts. In addition, cross talk due to capacitive coupling of long adjacent global interconnections, routing inefficiencies due to blockages of vias, and the repeaters required for the global interconnections are some other issues complicating the problem of improving the performance of global interconnects. Unfortunately, wiring schemes for global interconnection wires also tend to lag behind their shorter local and intermediate interconnection counterparts in terms of technological and performance improvements.
As a result of these and other issues, experts in the semiconductor industry have predicted a need to transition to unconventional solutions, such as optical technologies, to meet the substantial challenges that are expected to arise in the area of global intrachip interconnections. Background art examples of two systems that have been designed for such global intrachip interconnections are disclosed in papers from Professor Hugo Thienpont's research group at the Vrije Universiteit Brussels in Belgium are discussed below.
An optical interconnection system was outlined in a background art reference entitled “Demonstration of a Monolithic Micro-Optical Bridge for Free-Space Intrachip Interconnects,” by Thienpont et al. Thienpont et al. disclose a fabrication and proof-of-principle demonstration of a micro-optical interconnect bridge for intra-chip communication. However, the demonstration of Thienpont et al. used two levels of cylindrical lenses, and a retro-reflection scheme, and did not demonstrate the capability for arbitrary link configuration.
A second background art example is the paper entitled “Design of free-space microlens-relay optical interconnects: A focus on optical efficiency and scalability,” by Baukens et al. Baukens et al. modeled and compared the performances of different microlens-relay configurations. However, Baukens et al. only modeled and compared the reflection that occurs at a flat surface and only used micro-lenses and a retro-reflection scheme to achieve folded, on-axis links. In addition, the systems modeled by Baukens et al. did not include the capability for arbitrary link configuration.
Therefore, there is a need in the art for optical interconnect systems that can be applied to the problem of global interconnects and provide for arbitrary point-to-point free-space optical link configurations to meet the requirements of such global interconnects.